Modern electronic devices utilize semiconductor components, commonly referred to as “integrated circuits” which incorporate numerous electronic elements. These chips are mounted on substrates that physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be part of a discrete chip package, such as a single chip module or a multi-chip module, or may be a circuit board. The chip module or circuit board is typically incorporated into a large circuit. An interconnection between the chip and the chip module is commonly referred to as a “first level” assembly or chip interconnection. An interconnection between the chip module and a printed circuit board or card is commonly referred to as a “second level” interconnection.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as “input-output” or “I/O” connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial number of I/O connections.
The size of the chip and substrate assembly is a major concern. The size of each such assembly influences the size of the overall electronic device. Moreover, the size of each assembly controls the required distance between each chip and other chips, or between each chip and other elements of the circuit. Delays in transmission of electrical signals between chips are directly related to these distances. These delays limit the speed of operation of the device. For example, in a computer where a central processing unit operates cyclically, signals must be interchanged between the central processing unit chip and other chips during each cycle. The transmission delays inherent in such interchanges often limit the cycling rate of the central processing chip. Thus, more compact interconnection assemblies, with smaller distances between chips and smaller signal transmission delays can permit faster operation of the central processing chip.
The first level interconnection structures connecting a chip to chip module ordinarily are subject to substantial strain caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated with the chip tends to heat the chip and chip module, so that the temperatures of the chip and chip module rise each time the device is turned on and fall each time the device is turned off. Over a period of time, the device tends to undergo a number of heating up and cooling down cycles as the device is repeatedly turned on and off. These cycles, which cause an associated expansion and contraction of the device, are commonly referred to as “thermal cycling”. As the chip and the chip modules are ordinarily formed from different materials, having different coefficients of thermal expansion, the chip and the chip module ordinarily expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the chip module as the temperature of the chip and the chip modules changes. This relative movement deforms the electrical interconnections between the chip and the chip module and places them under mechanical stress. These stresses are applied repeatedly with repeated operations of the device, and can cause breakage of the electrical interconnections. Thermal cycling stresses may occur even where the chip and the chip module are formed from like materials having similar coefficients of thermal expansion, because the temperature of the chip may increase more rapidly than the temperature of the chip module when power is first applied to the chip.
In U.S. Pat. No. 5,627,405, which issued on May 6, 1997, Chillara discloses an integrated circuit assembly comprising an integrated circuit, a dielectric substrate and an anisotropic electrically conductive layer interposed between the dielectric substrate and the integrated circuit. The anisotropic electrically conductive layer is electrically conductive in directions that are parallel to an electrically conductive axis and is electrically insulative in other directions.
Commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,518,964; and 5,659,952; and commonly assigned U.S. patent application Ser. No. 8/365,699 filed on Sep. 5, 1996, the disclosures of which are hereby incorporated by reference herein, provide substantial solutions to the problems of thermal stresses. Nonetheless, alternative methods of addressing these problems are desired.